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CXA1386P/K
8-bit 75MSPS Flash A/D Converter
Description The CXA1386P/K are 8-bit high-speed flash A/D converter ICs capable of digitizing analog signals at the maximum rate of 75MSPS. The digital I/O levels of these A/D converters are compatible with the ECL 100K/10KH/10K. The CXA1386P/K is pin-compatible with the earlier models CXA1056P/K, CXA1016P/K, respectively. They can be replaced by the CXA1386P/K without any design changes, in most cases. Compared with the earlier models, these new models have been greatly improved in performance, by incorporating advanced process, new circuit design and carefully considered layout. Features * Differential linearity error: 1/2LSB or less * Integral linearity error: 1/2LSB or less * High-speed operation with maximum conversion rate of 75MSPS (Min.) * Wide analog input bandwidth: 150MHz (Min. for full-scale input) * Low Power consumption: 580mW (Typ.) * Single power supply: -5.2V * Low input capacitance: 17pF (Typ.) * Built-in integral linearity conpensation circuit * Low error rate * Operable at 50% clock duty cycle * Good temperature characteristics * Capable of driving 50 loads Pin Configuration Pins with name are NC pins (not connected).
LINV DVEE DGND (LSB) D0 D1 D2 D3 D4 D5 1 2 3 4 5 6 7 8 9 CXA1386P 28 AVEE 27 VRT 26 AVEE 25 AGND 24 VIN 23 AGND 22 VRM 21 AGND 20 VIN 19 AGND 18 AVEE 17 VRB 16 CLK 15 CLK 39 AVEE 40 AVEE 41 VRT 42 43 44 AVEE 1 2 3 LINV 4 DVEE 5 DGND1 6 DGND2 7
CXA1386P 28 pin DIP (Plastic)
CXA1386K 44 pin LCC (Ceramic)
Structure Bipolar silicon monolithic IC Applications * Digital oscilloscopes * HDTV (high-definition TVs) * Other apparatus requiring high-speed A/D conversion
38 37 36 35 34 33 32 31 30 29
AGND VIN AGND VRM AGND VIN AGND
CXA1386K
D6 10 (MSB) D7 11 DGND 12 DVEE 13 MINV 14
28 27 26 25 24 23 22 21 20 19 18
AVEE AVEE VRB
CLK CLK MINV DVEE DGND1
8 9 10 11 12 13 14 15 16 17
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
(LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 DGND2
E90114C54-ST
CXA1386P/K
Absolute Maximum Ratings (Ta = 25C) * Supply voltage AVEE, DVEE * Analog input voltage VIN * Reference input voltage VRT, VRB, VRM I VRT - VRB I * Digital input voltage CLK, CLK, MINV, LINV I CLK - CLK I * VRM pin input current IVRM * Digital output current ID0 to ID7 * Storage temperature Tstg Recommended Operating Conditions * Supply voltage AVEE, DVEE AVEE - DVEE AGND - DGND * Reference input voltage VRT VRB * Analog input voltage VIN * Pulse width of clock TPW1 TPW0 * Operating temperature Tc (CXA1386K) Ta (CXA1386P) Min. -5.5 -0.05 -0.05 -0.1 -2.2 VRB 6.6 6.6 -20 -20
-7 to +0.5 -2.7 to +0.5 -2.7 to +0.5 2.5 -4 to +0.5 2.7 -3 to +3 -30 to 0 -65 to +150 Typ. Max. -5.2 -4.95 0 +0.05 0 +0.05 0 +0.1 -2.0 -1.8 VRT
V V V V V V mA mA C Unit V V V V V ns ns C C
+100 +75
-2-
CXA1386P/K
Block Diagram
MINV
r1 VRT r/2 r r r 1 2 * * * 63 64 r 65 * * * 126 D5 Comparator
D7 (MSB)
r VIN
D6
r r r2 VRM r r
OUTPUT
D4
ENCODE LOGIC
127 128 129 * * * 191 192
D3
D2
r r VIN
D1
D0 (LSB)
r r r r3 r/2 193 * * * 254 255
VRB
CLK CLK
CLOCK DRIVER
LINV
-3-
CXA1386P/K
Pin Description and I/O pin Equivalent circuit Pin No LCC DIP Symbol I/O Standard voltage level Equivalent circuit Description Anlog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND or DGND 1/2. Analog VEE -5.2V (Typ.). Internally connected with DVEE (resistance: 4 to 6). Ceramic chip capacitors of at least 0.1F should be used to connect to AGND and be placed near the pins.
DGND (DGND1)
31, 33, 35, 37
19, 21, AGND 23, 25
--
0V
27, 28, 40, 41, 44
18, 26, 28
AVEE
--
-5.2V
23
16
CLK
r r CLK r r
CLK input
I 22 15 CLK
ECL
CLK
DVEE
r
r
Input complementary to CLK. With open connection, kept at threshold voltage (-1.3V). Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain the stable highspeed operation. Digital GND (Used for internal circuits and output transistors) Digital GND (Used for internal circuits) Digital GND (Used for output buffers)
--
3, 12
DGND
--
0V
5, 19
--
DGND1
--
0V
6, 16
--
DGND2
--
0V
-4-
CXA1386P/K
Pin No LCC DIP Symbol I/O
Standard voltage level
Equivalent circuit
Description Digital VEE Internally connected with AVEE (resistance: 4 to 6) Ceramic chip capacitors of at least 0.1F should be used to connect to DGND and be placed near the pins.
4, 20
2, 13
DVEE
--
-5.2V
DGND (DGND2)
8 9 10 11 12 13 14 15
4 5 6 7 8 9 10 11
D0 D1 D2 D3 D4 D5 D6 D7 O ECL
Di
LSB of data outputs. External pull-down resistor is required.
Data outputs. External pull-down resistors are required.
DVEE
MSB of data outputs. External pull-down resistor is required. Input pin for D0 (LSB) to D6 output polarity inversion (see output code table). With open connection, kept at "L" level.
-1.3V
DGND (DGND1)
3
1
LINV
I
ECL
r LINV or MINV r r
21
14
MINV
I
ECL
DVEE
r
Input pin for D7 (MSB) output polarity inversion (see output code table). With open connection, kept at "L" level.
-5-
CXA1386P/K
Pin No. LCC DIP Symbol I/O
Standard voltage level
Equivalent circuit
Description
AGND
VIN
32, 36
20, 24
VIN
I
VRT to VRB
VIN
Analog input pins. These two pins must be connected externally, since they are not internally connected. See Application Note for precautions.
AVEE
VRT
r1 r/2 r Comparator r Comparator r 2 * * * 127 128 129 130 * * * * * * * 255 1
26
17
VRB
I
-2V
Reference voltage (bottom) Typically -2V A ceramic capacitor of at least 0.1F and a tantalus capacitor of at least 10F should be used to connect to AGND and be placed near the pins. Reference voltage mid point be used as a pin for integral linearity compensation Reference voltage (top) Typically 0V When a voltage different from AGND is applied to this pin, a ceramic capacitor of at least 0.1F and a tantalus capacitor of at least 10F should be used to connect to AGND and be placed near the pins. Unused pins No internal connections have been made to these pins. Connecting them to AGND or DGND on PC board is recommended.
34
22
VRM
I
VRB/2
VRM
r2 r
Comparator Comparator r Comparator r Comparator
42
27
VRT
I
0V
VRB r3
r Comparator r/2
1, 2, 7, 17, 18, 24, 25, 29, 30, 38 39, 43
NC
--
--
-6-
CXA1386P/K
Electrical Characteristics Item Resolution DC characteristics Integral linearity error Differential linearity error Symbol n EIL EDL Fc = 75MSPS Fc = 75MSPS
(Ta = 25C, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V) Condition Min. Typ. 8 0.3 0.3 17 390 200 75 8 0 -1.13 Input connected to -0.8V Input connected to -1.6V 0 -50 7 Fc Taj Tds Tdo TPW1 TPW0 VOH VOL Tr Tf Error rate 10-9 TPS1 75 10 3.0 6.5 -1.50 50 50 110 18 10 155 32 24 0.5 0.5 Max. Unit bits LSB LSB pF k A mV mV V V A A pF MSPS ps ns ns ns ns V V ns ns MHz 46 40 dB dB TPS1 % deg mA mW
Analg input Analog input capacitance CIN Analog input resistance RIN Input bias current IIN Reference inputs Reference resistance Offset voltage VRT VRB Digital inputs Logic H level Logic L level Logic H current Logic L current Input capacitance Switching characteristics Maximum conversion rate Aperture jitter Sampling delay Output delay H pulse width of clock L pulse width of clock Digital outputs Logic H level Logic L level Output rising time Output falling time Dynamic characteristics Input bandwidth S/N ratio RREF EOT EOB VIH VIL IIH IIL
VIN = -1V + 0.07Vrms VIN = -1V
4.0 6.6 6.6 RL = 620 to DVEE RL = 620 to DVEE RL = 620 to DVEE, 20% to 80% RL = 620 to DVEE, 80% to 20% VIN = 2Vp-p Input frequency at -3dB Input = 1MHz, FS Clock = 75MHz Input = 18.75MHz, FS Clock = 75MHz Input = 18.749MHz, FS Error > 16LSB Clock = 75MHz NTSC 40IRE mod. ramp, Fc = 75MSPS -1.03
9.0
-1.62 0.9 2.1 150
{ {
Error rate
{
}
10-9 1.0 0.5 -150 -104 580
Differential gain error Differential phase error Power supply Supply current Power consumption2 1 TPS: Times Per Sample
DG DP IEE Pd
2 2 Pd = IEE * VEE + (VRT - VRB) RREF
-7-
CXA1386P/K
Output Code Table VIN Step D7 0V 0 1 MINV 1 LINV 1 D0 0 0 0 ****** 0 0 0 0 0 ****** 0 0 0 0 0 ****** 0 1 : : 0 1 1 ****** 1 1 1 0 0 ****** 0 0 : : 1 1 1 ****** 1 0 1 1 1 ****** 1 1 1 1 1 ****** 1 1 D7 0 1 D0 1 0 0 ****** 0 0 1 0 0 ****** 0 0 1 0 0 ****** 0 1 : : 1 1 1 ****** 1 1 0 0 0 ****** 0 0 : : 0 1 1 ****** 1 0 0 1 1 ****** 1 1 0 1 1 ****** 1 1 D7 0 1 1 ****** 1 1 0 1 1 ****** 1 1 0 1 1 ****** 1 0 : : 0 0 0 ****** 0 0 1 1 1 ****** 1 1 : : 1 0 0 ****** 0 1 1 0 0 ****** 0 0 1 0 0 ****** 0 0 1 0 D0 D7 0 0 D0 1 1 1 ****** 1 1 1 1 1 ****** 1 1 1 1 1 ****** 1 0 : : 1 0 0 ****** 0 0 0 1 1 ****** 1 1 : : 0 0 0 ****** 0 1 0 0 0 ****** 0 0 0 0 0 ****** 0 0
-1V
127 128
254 255 -2V VRT = 0V, VRB = -2V
Timing diagram
Tds N Analog input Tpw1 CLK CLK Tpw0 N+2 N+1
Digital output Tdo
N -1
80% 20% Tr
N
80%
N+1 20% Tf
-8-
CXA1386P/K
Electrical Characteristics Test Circuit Maximum conversion rate test circuit
Signal Source Vin CXA1386 P/K CLK CLK 8 ECL Latch + ECL Latch A B Comparator A> B Pulse Counter
fCLK - 1kHz 4 2Vp-p Sin Wave
DATA 16 Signal Source fCLK 1/4
Differential gain error test circuit Differential phase error test circuit
(CX20202A-1) VIN Amp 10 DUT CXA1386 P/K CLK NTSC Signal Source Delay VBB SG (CW) 50 Vector Scope DG.DP CLK 8 8
ECL Latch
10bit D/A
Integral linearity error test circuit Differential linearity error test circuit
+V S2 S1: ON when A < B S2: ON when A > B
S1
-V A< BA> B Comparator A8 to A1 A0 "0" DVM CLK (75MHz) Controller B8 to B1 B0
VIN
DUT CXA1386 P/K
8
8 Buffer
"1" 8 00000000 to 11111110
-9-
CXA1386P/K
Power Supply Current Test Circuit Analog input bias current test circuit
-1V
A
IIN -1V IIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 CXA1386P
28 27 26 25 24 23 22 21 20 19 18 17 16 15 -2V
A
39 40 41 42 43 44 1 2 3 4 5 6 7 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
-2V
CXA1386K
8 9 10 11 12 13 14 15 16 17
A IEE A IEE
-5.2V -5.2V
Sampling delay test circuit Aperture jitter test circuit
37.5MHz Amp OSC1 : Variable VIN fr CLK OSC2 ECL Buffer 37.5MHz CXA1386 P/K 8 Logic Analizer
Aperture jitter test method
0V VIN -1V -2V
CLK v t VIN 1024 samples 129 128 127 126 125 (LSB)
t
CLK
Aperture jitter
Aperture jitter is defined as follows: Taj = / 256 = /( t 2 x 2f ),
Where (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point.
- 10 -
CXA1386P/K
8bit 75MSPS ADC and DAC Evaluation Board It is necessary to equip "the CXA1396D/P EVALUATION BOARD WITH DAC" with "A1396D - A1386P ADAPTER" in order to evaluate CXA1386P. In addition to indispensable features such as the reference voltage generator, this tool equips two sets of analog inputs (the direct input and the buffer amplifier input), the input voltage offset generator, the clock decimator, the output data latches, the 10-bit high-speed DAC, and the 20-pin cable connector for digital outputs. This evaluation board provides full performance of the CXA1386P and it is designed to facilitate evaluation. Features Resolution: 8bits Maximum conversion rate: 75MSPS Supply voltage: +5.0V, -5.2V, -2.0V Two analog inputs (Direct input, buffer amplifier input) Clock level converter: Sine wave to ECL level signal Reference voltage adjustment circuit for the A/D converter Built-in clock frequency decimation circuit: (1/1 to 1/16)
Fig. 1. Block Diagram
-5.2V (A) VR2 (2k) VRB -2V
H
L
-5.2V (A) VR1 (2k) Vin OFFSET
VR3 (1k)
SW1
SW2 DIGITAL OUT (CONNECTOR) (D7 to D0) 8
LINV MINV VRB J1 A 1k B CLK C Vin CLK X (-2) D (D7 to D0) 8 8 VRM CXA1386P DATA LATCH 8 BUFFER
AMP.IN 240 51
2 (CLK.CLK)
51
DIR.IN
0.1 CLK DECIMATOR CLK SW3 1/1 to 1/16 +5V -5.2V (A) AGND -5.2V (D) DGND
D/A CONVERTER
D/A OUT
-2V (D)
- 11 -
CXA1386P/K
Supply Current Item -5.2V +5.0V -2.0V Min. Typ. 0.85 15 0.45 Max. 1.0 30 0.6 Unit A mA A
(Note: Supply current -2.0V is the value when Rn10, Rn11 and Rn12 are not mounted.)
Analog Input (DIR. IN, AMP. IN) Item Input voltage (DIR. IN) (AMP. IN)1 Input impedance (1: Adjustable by VR1) Min. -2.0 -0.5 50 Typ. Max. 0 +0.5 Unit V V
Clock Input (CLK) Item Input voltage (Peak to Peak) Input impedance Min. Typ. 2.0 50 Max. Unit Vp-p
Digital Output (D0 to D7) ECL 10KH level Clock Output ECL 10KH level, complementary output Output Code Table MINV LINV 0V : : : : : : : : -2V 0 0 1 1 1 ****** 1 1 1 1 1 ****** 1 0 : : 1 0 0 ****** 0 0 0 1 1 ****** 1 1 : : 0 0 0 ****** 0 1 0 0 0 ****** 0 0 0 1 1 0 0 ****** 0 0 1 0 0 ****** 0 1 : : 1 1 1 ****** 1 1 0 0 0 ****** 0 0 : : 0 1 1 ****** 1 0 0 1 1 ****** 1 1 1 0 0 1 1 ****** 1 1 0 1 1 ****** 1 0 : : 0 0 0 ****** 0 0 1 1 1 ****** 1 1 : : 1 0 0 ****** 0 1 1 0 0 ****** 0 0 1 1 0 0 0 ****** 0 0 0 0 0 ****** 0 1 : : 0 1 1 ****** 1 1 1 0 0 ****** 0 0 : : 1 1 1 ****** 1 0 1 1 1 ****** 1 1
VIN
- 12 -
CXA1386P/K
Fig. 2. Timing Chart
N A/D input pin Vin (DIR. IN, AMP. IN) N+1
PCB input pin
CLK
CLK A/D clock CLK
A/D output
D7 to D0
N -1
N
D7 to D0 PCB output pin (For 1/1 frequency division)
N -2 Tdh 1.8ns (Typ)
N -1
N
CLKN PCB output pin CLK (For 1/1 frequency division)
PCB output pin DATA OUT (For 1/2 frequency division)
N -4
N -2 Tdh 1.8ns (Typ)
N
CLKN PCB output pin CLK (For 1/2 frequency division)
Adjustment Methods and Notes on Operation 1) Vin Offset (VR1) The volume to adjust the signal range (0V center assumed) with the A/D converter input range when a waveform is input through AMP. IN. 2) A/D Full Scale (VR2) The volume to adjust A/D converter VRB voltage. 3) Linearity (VR3) The volume to adjust VRM (linearity) voltage.
- 13 -
CXA1386P/K
4) D/A Full Scale (VR4) The volume to adjust D/A output full scale (-1V) 5) J1 (input selection) A: Shorts to adjust VRM voltage. B: Shorts to supply DC voltage to Vin. C: Shorts to select AMP.IN input. D: Shorts to select DIR. IN input. [Jumper Poisition at shipment] J1 A B C D
6) SW1 The switch for LINV High/Low 7) SW2 The switch for MINV High/Low 8) SW3 (Decimation) The switch to select clock frequency decimation. Switch position: decimation ratio 0: 1/1 1: 1/2 2: 1/4 3: 1/8 4: 1/16 9) SW4 (D/A INV) The switch for D/A converter output inversion. 10) Rn10, Rn11 and Rn12 are not mounted at shipment. They are not required during evaluation. 11) Waveform probe pins P5 and P8 through P28 are devised to facilitate GND connection in order to reduce the distortion. As shown in the diagram below, the distance between the probe point and the GND is 300 mils, and there is 1.2mm throughhole at each. The signal and GND locations are suit for a Tektronix GND tip (part number 013-1185-00).
1.2mm GND 300mil Probe point
Fig. 3. 12) D/A converter (IC13) input data (waveform probe pins P21 through P28) are the complementary signals of the decimated A/D converter outputs. Those are inverted again in the D/A converter so that the direction of reproduced waveform can agree with the A/D input signal converter. 13) The part number of the digital output connector is KEL 8830E-020-170S. A corresponding connector and cable assembly is JUNKOSHA KB0020MCG50BI.
- 14 -
Rn6 Rn6 75 -2V (D) CONNECTOR C53 0.1 DGND Rn12 Rn12 DGND 51 Rn12 51 Rn12 51 Rn11 51 Rn11 51 Rn11 51 Rn11 51 Rn11 -2V (D) DGND Rn10 -2V (D) Rn5 Rn5 75 75 Rn10 75 Rn10 75 Rn10 75 Rn10 C51 0.1 C40 0.1 C26 1 DGND -2V (D) DGND -2V (D) DGND P34 +5V (A) +5V (A) C57 33 AGND D2 P12 Rn3 Rn3 75 Rn3 75 FERRITE BEAD -5.2V (A) Rn3 75 Rn3 75 -5.2V (D) DGND DGND C35 0.1 C24 0.1 P13 D3 P33 AGND 17 CLK 9 D4 5 D2 7 D3 3 D1 51 Rn12 1 D0 2 DGND 4 DGND 6 DGND KEL: 8830E-020-170S (TOP VIEW)
Fig. 4. PCB Circuit Schematic
FERRITE BEAD P9 P8 CLK CLKN R17 51 CLK 21 Rn6 75 Rn6 75 Rn6 75
+5V (A)
C9 0.1
VRB P2
22 NC
CLKN 20 NC 19 C25 0.1 C22 R16 0.1 51 -2V (D) DGND DGND
1 VCC1 1
DGND VCC2 16
VCC2 16 VCC1 Aout_ Dout_ 15 Bout_ Cout_ 14 Ain Din 13 COM IN 12 Cout 11 Cin 10 Dout 9 C52 0.1 Aout Bout Bin VEE Q5 15 DGND -2V (D)
AGND
Q1 2SA970
Linearity
VR3 1k
C19 0.1
AGND C20 10
23 VRB 2 3 4 Q2 4 5
CLK P18 C41 0.1 D7 Rn4 Q3 13 D5 12 D4 11 Q1 Q4 14
Q0
C42 0.1 DGND
2 3
24 NC
MINV 18 P16 P17 D6 DVEE 17 C27 0.1
R9 1.3k AGND A/D Full Scale VR2 2k IC10 : 10H176 IC12 : 10H101
AGND
AGND
68 7 5 4 IC1-2 IC3 TL4558 TL431CP
C18 0.1
25 AVEE 5 6 7 D2 7 8
-5.2V (D) D3 10 CLK 9 D1 D0
-5.2V (A) R5/11k DGND1 16 P17 -5.2V (D) Rn4 75 Rn4 75 DVEE DGND Rn4 75
R6 240
26 AVEE 6
P1
Vin Offset DGND2 15 D7 14 D6 13 P14 D4 -2V (D) DGND DGND -5.2V (D) D5 C36 C26 0.1 0.1 DGND R19 51 P15 D5 12 D4 11 D3 10 D2 9 D1 8 D0 7 DGND2 6 DGND1 5 DGND C25 0.1 P6 DGND Rn5 75 Rn5 75 Rn5 75 Rn4 75
R8 510 VR1 2K
VRM C8 0.1
-5.2V (A)
27 NC
2 3
R4 22k 61
R7 1k
-5.2V (A)
AGND
28 NC 8 VEE
8 DGND 10 DGND 12 11 D5 DGND 13 D6 15 D7 14 DGND
AGND
+5V (A)
29 AGND
4 C3 IC1-1 TL4558 0.1
C4 3.3
AGND
30 VIN
AGND
AGND AGND
C7 1
C12 0.1
31 AGND
16 DGND 18 DGND 19 CLKN 20 DGND DIGITAL OUT DGND
AGND AGND
R13 1k
A
32 VRM
R2 240
AMP.IN
2 3
7
6
R10 R11 510 43
B
C17 0.1
C
33 AGND
R1 51
D
AGND
J1
34 VIN
35 AGND
AGND
4 IC4 CLC404AJP R12 C6 51 1 AGND C11 0.1
AGND P4
36 NC
-5.2V (A)
AGND
AGND AGND
AVEE P3
37 NC 1 VCC1 1 2 3 4 5 6 7
C39 0.1 DGND VCC2 16 VCC1 Q5 15 DGND Q4 14 Q3 13 D5 12 D4 11 D3 10 CLK 9
38 AVEE
DVEE 4
CXA1396D - CXA1386P ADAPTER
AGND AGND
VIN P5
VCC2 16
-5.2V (A)
DIR.IN LINV 3 NC 2 C24 0.1 -5.2V (D)
39 AVEE 2 3 4 Q2 5 6 7 D2 8
VEE D1 D0 Q1 Q0
Aout_ Dout_ 15 DGND Bout_ Cout_ 14 Ain Aout Bout Bin Din 13 COM IN 12 Cout 11 Cin 10 AGND
C15 1
C16 0.1
40 NC
AGND AVEE 1
41 VRT
AGND
IC9 : 10H176
IC11 : 10H101
AGND
42 NC
P32 -5.2V (A) -5.2V (A) C56 33 AGND
IC2 : 10H116
IC5 : 10H136
IC7 : 10H164
6 7 S2 7 8
-5.2V (D) VEE A Cin_ 10 S1 9 C37 0.1 DGND DGND DGND C22 C21 0.1 0.1 C 10 B9
Bout_
VBB 11
Rn1 51 -2V (D) D1 11
R18 51
C31 0.1 -2V (D) DGND
IC8 : 10H116
C2 0.1
7 Bout 8 VEE
-5.2V (D)
Bin 10
8 VEE
Bin_ 9
Rn1 51
C10 0.1
C13 0.1
C14 0.1
7 Bout 8 VEE
C29 0.1 DGND C30 0.1 DGND SW3 Decimation C34 0.1 DGND -5.2V (D)
Bin 10 Bin_ 9
R20 51 C38 0.1 DGND -2V (D)
D0 P21
75 Rn8 75 Rn8 C44 0.1
IC13 : CX20202A-1
- 15 -
P10 P11 D1 -2V (D) DGND D1 H DGND -5.2V (D) L D2 D3 R15 330 D0 SW1 LINV SW2 MINV -2V (D)
8
VEE -5.2V (D)
Dout 9
P31 -5.2V (D) -5.2V (D) C55 33 DGND P30 DGND DGND DGND P29 -2V (D) -2V (D) -2V (D) C45 0.1 Rn9 DGND D7 P28 D6 P27 Rn9 75 Rn9 C54 33 DGND R22 C49 240 0.1
1 MSB AGND2 28 2 D2 1 VCC1
VCC2 16 DGND DGND 75 Rn9
1 VCC1 1
DGND DGND 2 DGND Rn2 Enable_ X3 X2 X1 X0 X4 11 X5 12 X6 13 X7 14 Z 15 DGND
VCC2 16
1 VCC1 2 3 4 Cout_ 4 5 6 5 6
D2 D3 D0 12 R14 51 Rn2 51 CLK 13 Rn2 51 Q3 Q0 14 Q2 Q1 15 DGND
VCC2 16 VCC
C23 0.1 VCC1 16
R21 C48 0.1 VR4 1k VREF 27 2k
AGND C50 33
DGND
DGND
3 D3 2 Aout_ 3
Aout Cout 15 Cout_ 14 D5 P26 D4 P25 75 Rn9 75
AVEE 26
2 Aout_ 3
Cout 15
4 D4
Rn8
D/A Full Scale IC14 NC 25 TL431CP
-5.2V (A)
3
Aout
Cout_ 14
5 D5 4 Ain_ 5 Ain 6
Cin 13 Cin_ 12 Bout_ VBB 11 C37 0.1 DGND D3 P24 D2 P23 D1 P22 75 Rn8 75 Rn8
NC 24
C1 0.1
4 Ain_
Cin 13
CLK
R3 51
5 Ain
Cin_ 12
Rn1 51
6 D6 7 D7 8 D8 9 D9 10 LSB
DGND -2V (D) Rn7 CLKN P20 CLK P19 51 Rn7 51 Rn7 51 Rn7 C43 0.1 DGND 51 Rn7 -2V (D) DGND
NC 23 NC 22 NC 21 OUT 20 NC 19 D/A OUT
DGND
Rn1 51
Rn2 51 Rn2 51
Rn1
DGND
-5.2V (D)
C5 0.1 -2V (D) DGND
DGND
DGND DGND
11 NC 12 NC
AGND1 18 DGND 17
AGND AGND DGND SW4 D4 D/A INV L DGND
13 CLKN 14 CLK
INV 16 DVEE 15 C46 0.1 C47 0.1 -5.2V (D) DGND DGND D5 D6 H R23 3.2k -5.2V (D)
CXA1386P/K
CXA1386P/K
Characteristics Graphs
Fig 5. CXA1386P SNR vs. Input Frequency
50 CLK = 75MHz, VEE = -5.2V 45
SNR [dB]
40
35
30
25
1
10 Input Frequency [MHz]
100
Fig. 6. CXA1386P Effective Bits vs. Input Frequency
8.0 CLK = 75MHz, VEE = -5.2V 7.0
Effective Bits [bit]
6.0
5.0
4.0
1
10 Input Frequency [MHz]
100
Fig. 7. CXA1386P 2nd, 3rd Harmonic Distortion vs. Input Frequency
-20 CLK = 75MHz, VEE = -5.2V
2nd, 3rd Harmonic Distortion [dB]
-30
-40
-50
2nd Hmnc
-60 3rd Hmnc -70 1 10 Input Frequency [MHz] 100
- 16 -
CXA1386P/K
CXA1396D - CXA1386P ADAPTER (SCALE = 2/1)
55mm
CXA1386P ADAPTER
28
15 35mm
1
14
TOP VIEW
- 17 -
CXA1386P/K
Parts Layout
- 18 -
CXA1386P/K
Printed Pattern
1st layer Component plane (Top View)
4th layer Solder plane (Top view)
- 19 -
CXA1386P/K
2nd layer GND plane (Top View)
3rd layer Power supply plane (Top View)
- 20 -
CXA1386P/K
Package Outline CXA1386P
Unit: mm
28PIN DIP (PLASTIC) 600mil
+ 0.1 0.05 0.25 -
15
+ 0.4 37.8 - 0.1
28
+ 0.3 13.0 - 0.1
1 2.54
14
0.5 0.1 1.2 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-28P-03 DIP028-P-0600-C LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER 4.2g
CXA1386K
44PIN LCC (CERAMIC) 1.8g
C 1. 01
3.0 MIN
0.5 MIN
+ 0.4 4.6 - 0.1
15.24
0 to 15
12.7 0.1 1.951 0.25 1.905 0.25
R0.2
8
12.5 0.2
1.27
0.635 0.07
PIN NO.1 INDEX
2.159 0.5
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LCC-44C-01 QFN044-C-S650-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 1.8g CERAMIC GOLD PLATING
- 21 -
1.651 0.18
0.3
1.27 0.1
C
0.
50
+ 0.35 16.51 - 0.25
6

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